Within an integrated circuit, a clock signal is distributed to clocked circuits, e.g., flip-flops, configured as pipeline registers and other storage resources. The clock signal is typically distributed to the clocked circuits through a clock tree that includes multiple buffers configured to limit the fanout of each buffer and ensure that the timing characteristics of the clock signal are maintained within a predetermined range so that the integrated circuit operates properly. The number of buffers in the clock tree increases as the load presented to the clock signal by the clocked circuits increases. The amount of power consumed by the clock tree increases as the size of the dock tree increases. Increased power consumption is particularly undesirable, particularly for integrated circuits used in portable devices because the time between recharging the battery is reduced.
There is thus a need for managing the load presented to the clock signal by the clocked circuits within an integrated circuit and/or addressing other issues associated with the prior art.